Semiconductor Engineering

Post Layout Simulation Is Becoming The Bottleneck For Analog Verification

My, have times changed. I remember when I first started out as a green analog designer right out of college, we would cut rubylith masking film on a large light table representing the different layers ...
Semiconductor Engineering

Detecting Hardware Trojans In a RISC-V Core’s Post-Layout Phase

A new technical paper “Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans – A RISC-V Case Study” was published by researchers at University of Bremen, DFKI GmbH, and the German ...
EDN

Taking the Guesswork Out of DDR Design with Integrated Schematic, Layout and Simulation Tools

DDR memory is quickly becoming not only the leading technology but the only technology used in memory design. As such, DDR systems are in high demand in the tech industry. High-speed simulation tools ...
EDN

Silicon Frontline Technology, Founded by EDA Technologists, Announces Post-Layout EDA Verification Software

Los Gatos, CA – May 12, 2009 – Silicon Frontline Technology, Inc. (SFT), a new company founded by Electronic Design Automation (EDA) technologists, today announced the company and its first products ...
Design-Reuse

A point of view on ''Analog Design and Layout Migration automation in the AI era''

The design teams typically invest years and numerous iterations to validate IP and produce a functioning chip. Once this validation is complete, they create derivatives of the silicon-proven IP, often ...