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Samsung touts 96% lower-power NAND design — researchers investigate design based on ferroelectric transistors

Samsung researchers have published a detailed account of an experimental NAND architecture that aims to cut one of the technology’s largest power drains by as much as 96%. The work — Ferroelectric ...
ExtremeTech

New manufacturing technology enables vertical 3D NAND transistors, higher capacity SSDs

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동아사이언스

Ferroelectric transistor design promises major power savings for future NAND flash

As the scale of artificial intelligence (AI) models grows rapidly, securing the performance of memory semiconductors has become a key issue. NAND flash, a type of memory semiconductor with much larger ...
EDN

How can 3D FeFETs substitute NAND flash for low-latency storage

The part 1 of this two-article series outlined the NAND flash technology and how it transitioned from 2D to 3D NAND flash. The article also explained the current challenges in the way of density ...