EDN

The CS4350 PLL DAC Simplifies System Design

Typical Digital to Analog Converters (DACs) require a high-speed Master Clock to clock their digital filters and modulators, as well as some portions of their discrete time analog circuitry. This ...
Electronic Design

All digital phase-locked loop offers sub-mW power consumption

San Francisco, CA. At the 2017 International Solid-State Circuits Conference in San Francisco, imec, Holst Centre, and ROHM presented an all-digital phase-locked loop (ADPLL) for Internet-of-Things ...
Electronic Design

Digital PLL Perks Up Performance In T1-E1, Other TDM Apps

Thanks to a digital phase-locked loop (DPLL), the ZL30109 DS1/E1 System Synchronizer chip brings timing and synchronization to multitrunk DS1 and E1 transmission equipment. DPLLs typically use a DSP ...
EDN

PLL design kit features timing models, GDSII physical views

A new design kit enables system-on-chip (SoC) developers to efficiently incorporate clocking IP into their designs with full support for layout, simulation, and timing closure. Perceptia Devices, an ...
EurekAlert!

Combating fractional spurs in phase locked loops to improve wireless system performance in Beyond 5G

Two innovative design techniques lead to substantial improvements in performance in fractional-N phase locked loops (PLLs), report scientists from Tokyo Tech. The proposed methods are aimed to ...